Recently, with small-sizing and increasing the performance of electronic instruments, small-sizing and thinning, increasing the performance, and high reliability have been required for semiconductor devices constituting electronic instruments and multilayer print wiring substrates for mounting them. Due to those requirements, the mounting method is shifted from a pin-insertion type packing to a surface mounting type packaging. Recently, a mounting method called bare chip mounting which directly mounts a semiconductor chip on a printed substrate has been investigated. Also, with increasing the number of pins of a semiconductor chip, the necessity of using a multilayer of a substrate for mounting the semiconductor element has been increased. A method of forming a multilayer substrate is proposed, wherein a multilayer wiring substrate of a build-up system is formed by alternately piling up each insulating layer using a photosensitive resin and each conductive layer formed by plating or a vapor deposition, on one surface or both surfaces of a substrate. However, such a multilayer wiring substrate has the problems that the production steps are complicated, the number of steps is increased, the yield is low, the time of delivery is long, and the like. Also, a method of forming a multilayer substrate by forming an electrically conductive paste as projections by dispenser, etc., on one surface (copper-clad surface) of a glass and epoxy one-surface copper-clad laminate plate, laminating an adhesive sheet and a copper foil thereon, pressing the assembly, and repeating the procedure is proposed as disclosed in JP-A-8-288649 (the term "JP-A" as used herein means an "unexamined published Japanese patent application"). However, this method has problems in the reliability of connection, the connection resistance, etc. This method also has various problems that it is difficult to apply to fine circuits and also it is necessary to repeat pressing the required number of the layers for the formation of a multilayer structure, which requires increased time for the production.
On the other hand, the bare chip mounting involves adhering a silicon chip having a thermal expansion coefficient of from 3 to 4 ppm/.degree. C. to a printed substrate having a thermal expansion coefficient of from 10 to 20 ppm/.degree. C. directly via an adhesive. Therefore, a problem arises that a stress is applied due to the difference in the thermal expansion coefficients, thereby decreasing the connection reliability. Further, the stress causes the problem such that cracks occur in the adhesive to decrease moisture resistance. To relax such a stress, a method of, for example, attempting diffusion of the stress by decreasing a modulus of elasticity of the adhesive have been practiced. However, even by these methods, the connection reliability cannot sufficiently be ensured, and to ensure a higher connection reliability, it is necessary and indispensable to decrease the thermal expansion coefficient of the substrate itself. To overcome this problem, a multilayer wiring substrate using a Ni--Fe alloy as a plate and alternately piling up thereon each insulating layer and each wiring conductor, or a multilayer wiring substrate obtained by forming a solder pad on the surface layer of the above-described multilayer wiring substrate by a photoetching method followed by heat-pressing to integrate them in a body is proposed as disclosed in JP-A-61-212096.
However, when copper is used as the wiring electric conductor in these multilayer wiring plates, the modulus of elasticity of the copper is very large as compared with the modulus of elasticity of a polyimide resin constituting the insulating layer. Therefore, it is difficult to decrease the thermal expansion coefficient of the entire multilayer wiring plate as that of silicon constituting a semiconductor chip. Also, since a metal thin-film forming technique such as a vapor deposition method, a sputtering method, etc., is used, the productivity is low and the production cost increases. Furthermore, a solder pad is formed by a vapor deposition method or a photoetching method, so that a complicated step is required.